DC-to-DC converters function as “power converters” by changing a source of direct current from an input voltage level to a desired output voltage level. Certain types of DC-to-DC converters also find use in synchronous rectification and other applications. While the term “DC-to-DC converter” broadly encompasses both linear-mode converters and switched-mode converters, the term is used herein to particularly connote switched-mode converters.
One type of switched-mode converter accomplishes the desired voltage conversion by temporarily storing energy taken from the input voltage source in the magnetic field of an inductor or transformer and then releasing the stored energy at the output of a switching circuit that includes the inductor or transformer. The switching circuit generally includes high-side and low-side switching elements (e.g., power MOSFETs) used for accomplishing the timed energy storage and release cycles. The switching element may be integrated into the DC-to-DC converter, or it may have an output drive stage, for driving external switching elements.
DC-to-DC converters generally can be configured as step-down converters (“buck”) that provide an output voltage lower than the input supply voltage, or they may be configured as step-up (“boost”) converters that boost input voltage. Moreover, DC-to-DC converters come in a wide variety of control topologies. Here, the term “control topology” denotes the particular control scheme adopted by the DC-to-DC converter for controlling its output voltage generation. The term therefore connotes the control logic and/or may connote the particular feedback circuitry used by the DC-to-DC converter for monitoring output voltage and/or output load conditions.
In some respects, the particular control topology used in a given application may be dictated by design constraints or specified performance requirements. However, in a broad sense many DC-to-DC converter applications require high efficiency while operating over a wide load range. Consider, for example, the capacity-limited batteries used in cellular telephones and other small consumer electronic devices. In those contexts, efficiency may not be the paramount design consideration but it is almost always key to obtaining the longest possible operating time from a given level of battery charge.
One widely used method of achieving such efficiency involves the use of a DC-to-DC converter control topology termed “constant on-time” or “COT.” In an example COT topology, illustrated by known COT DC-to-DC converter 10 in FIG. 1. The illustrated converter 10 provides load current to a load 12 (e.g., a DC-powered circuit or device) at a desired voltage VOUT, based on a COT controller 14 driving an H-bridge switching circuit that includes two MOSFETs, Q1 and Q2, and an output inductor L.
The controller 14 includes Q1 and Q2 drivers 16 and 18 for switching the MOSFETs Q1 and Q2, respectively, and further includes an on-time pulse generator 20 for generating high-side and low-side pulses to control the on-off switching of Q1 and Q2 via the drivers 16 and 18. The controller 14 further includes an on-time comparator 22 that triggers the on-time pulse generator 20 responsive to a feedback signal generated by a feedback circuit 24 used for monitoring the output voltage VOUT.
One also sees a program resistor 26 that is used to set the constant on-time of the high-side pulses generated by the on-time pulse generator 20 for the Q1 driver 16, which will be understood to be the “high-side” switch driver. This designation arises because the Q1 MOSFET connects the switched inductor L1 to the input supply voltage V. Conversely, the Q2 driver 18 is referred to as the “low-side” switch driver because it controls switching of the Q2 MOSFET, which connects the switched inductor L1 to signal ground.
A “switching cycle” in this regard includes a time during which Q1 is switched on (“conducting”), while Q2 is off (not conducting), followed by a time during which Q2 is switched on and Q1 is off. The time that Q1 conducts during each cycle is termed the “on-time” (TON) and the COT topology holds that on-time substantially constant, at least for a given input-output voltage relationship. Indeed, the hallmark of the COT converter topology is that the width of each on-time pulse does not vary for a given set of VIN/VOUT conditions. (Here, the term “does not vary” must be understood in a common sense fashion, meaning that small, unintended variations in on-time may occur, but the operating aim of the COT topology is to hold TON constant from switching cycle to switching cycle.) With this approach, the COT-based converter accomplishes regulation of VOUT by varying the conduction time of the low-side switch Q2.
See FIG. 2 for known control and operation signals for the converter 10 of FIG. 1. In the diagram, a high state for the Q1 and Q2 drive signals equals “ON,” while a low state equals “OFF.” One therefore sees that Q2 is driven OFF when Q1 is driven ON, and vice versa. Moreover, one sees that the high-side pulse width on time (TON) is held constant. FIG. 2 also shows the inductor current waveform corresponding to the Q1/Q2 switching control. (Note that FIG. 2 assumes steady-state load conditions and one therefore does not see any variation in the on-time of the low-side pulses driving Q2, but it will be understood that regulation control of VOUT is effected by varying the low-side pulse on-time.)
In a known approach to COT-based control, the constant on-time TON of the high-side pulses used to drive the Q1 transistor is set according to the following equation:
            T      ON        =                            V          OUT                          V          IN                    ·      K        ,where VOUT is the target output voltage—i.e., the regulated voltage to be maintained at the output of the switching circuit—and where VIN is the input supply voltage and K typically is a value that can be set by the circuit designer (perhaps within a defined range). See, for example, the program resistor 26 of FIG. 1, where the resistance value chosen determines the value of K.
The COT control method makes it relatively easy to operate in a power saving mode at light loads. To implement power saving mode, a COT-based controller inserts additional “dead time” into the switching cycle, during which neither the high-side switch Q1 nor the low-side switch Q2 is conducting—i.e., both switches are “OFF” during the dead time. See the example diagram of FIG. 3, which illustrates dead time insertion. The dead time insertion technique extends the overall switching cycle and therefore reduces the switching frequency, which reduces the switching losses associated with the high-side and low-side switches Q1 and Q2. The power saving mode thus yields higher efficiency at light loads.
The SEMTECH CORPORATION sells an exemplary COT-based converter, identified as the “SC418ULTRT.” A detailed data sheet is available for this part and it explains general aspects of COT-based control, along with providing specific design and performance information for the SC418ULTRT.
One characteristic of heretofore known approaches to COT-based control is that the constant on-time TON generally is programmed or otherwise set at design time and is fixed during converter operation (for fixed input/output voltage conditions). This approach causes significantly increased output voltage ripple during light load conditions. Consider that during any switching cycle, the inductor current exceeds the load current for part of the cycle. The output capacitor COUT (see FIG. 1) absorbs the excess current flowing from the inductor, creating a voltage ripple at the capacitor. At high load currents when the converter operates in “continuous conduction mode” (CCM), the inductor current ripple is centered on the load current.
The diagram of FIG. 4 illustrates this condition. As shown in the diagram, such operation results in a net charge flowing into and out of the capacitor during the switching cycle. For the CCM case, where at all times one of the two transistors Q1 and Q2 is on except for inherent dead-time delays at on/off transitions edges, the net charge, ΔQCCM, absorbed by the output capacitor can be expressed as:ΔQCCM=(TON)2·(VIN/VOUT)·(VIN−VOUT)/(8·L).where L is the inductance of the switched inductor in Henrys.
At light load currents, the inductor current is not centered on the load current. If the load current is near zero, the net charge absorbed by the output capacitor is much higher. Refer to the example diagram in FIG. 5. The higher net charge results in higher output ripple voltage. For this no-load case (or for near-zero loads) the net charge, ΔQNL, absorbed by the output capacitor can be expressed as:ΔQNL=(TON)2·(VIN/VOUT)·(VIN−VOUT)/(2·L).Comparing these equations, one sees that ΔQNL is four times the value of ΔQCCM. This increase nominally results in a corresponding fourfold increase in output voltage ripple at light loads, although the actual increase depends on several issues, such as the characteristics of output capacitor used.